Institute for Development and Research in Banking Technology, IDRBT

• First-class regular BE/BTech/ME/MTech in CSE/IT/ECE or any other directly related streams from a recognised Institute with a consistently good academic record throughout
• Qualified CSIR-UGC NET or GATE in Computer Science or Electronic & Communications.
• Preference will be given to candidates interested in pursuing their Ph.D

Essential Skills:

• The candidate should have hands-on knowledge of HLS and RTL tools
• Knowledge in RTL synthesis algorithms, datapath or high-level synthesis
• Knowledge in FPGA architecture, VHDL and Verilog based design
• Strong communication skills and a quick learner